1. Field of Invention
The present invention relates to a flip chip package structure. More particularly, the present invention relates to a flip chip package structure having an improved reliability in the connection between the chip and the substrate inside the package.
2. Description of Related Art
The fabrication of integrated circuits (IC) in the semiconductor industry can be roughly divided into two major stages: an integrated circuit (IC) fabrication stage and an IC packaging stage. In general, a chip is an end product of a series of operations on a wafer including ion doping, circuit laying, dielectric-layer depositing and wafer dicing. After the production of a chip, a packaging operation is performed such that the chip is electrically connected to a substrate through conductive wires or bumps, for example. By packaging the chip, the chip as well as the electrical connection between the chip and the substrate is protected.
As the level of integration for the integrated circuits increases, a variety of packaging structures for the chip has been developed. Flip chip bonding is one of the techniques capable of reducing chip package area and shortening overall transmission paths. At present, flip chip bonding is widely adopted in the chip packaging arena to produce packages including the chip scale packages, direct chip attached (DCA) packages and the multi-chip module (MCM) packages.
In a conventional flip chip bonding process, a plurality of bumps are first attached to the bonding pads on a chip. Thereafter, a screen-printing method is used to deposit some solder material on the contacts of a substrate. The chip is then flipped over and the bumps on the chip are dipped into the solder material above various contacts. A reflow process is performed so that the solder material is able to combine with the bumps to form a plurality of bump blocks. Through the bump blocks, the chip not only is firmly attached to the substrate but is also electrically interconnected as well.
Some problems are often found in the aforementioned flip chip bonding process, for example: 1. Since the solder is a paste-like material, the bumps can hardly stand firmly over the contacts of the substrate after the bumps are attached on the solder positioned on the contacts of the substrate. If the substrate is subjected to a random external force, for example, by transportation or by some air current inside a reflow oven, the bumps may be shifted out of the desired contact position. 2. Since the difference in the coefficient of thermal expansion between the chip and the substrate is generally large, the substrate is likely to warp when subjected to heat. Ultimately, some of the bumps attached to the peripheral region of the chip may peel off from the substrate leading to a drop in the reliability of the electrical connection between the chip and the substrate. 3. The reference expansion point—where, in an ideal case, there is no stress due to thermal expansion between the chip and the substrate—does not always fall in the central region of the chip. If the reference expansion point is on one side of the chip, the bumps on the other side of the chip will be subjected to a larger stress and deformation. When the stress on this side of the chip exceeds a permitted range, the bumps will peel off from the substrate.